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Altera University Program Audio core
https://people.ece.cornell.edu/land/courses/ece5760/DE1_SOC/Audio_core.pdf
The Audio core facilitates the transfer of audio data with the Audio CODEC chip on the Altera DE-series boards. Data is transferred serially between the FPGA and the CODEC. However, data written/read to/from the Audio core is transfered in a parallel manner. The Audio core automatically serializes/deserializes the data.
Audio/Video Configuration Core for DE-Series Boards
http://ee.sharif.edu/~microlab_t/micro/Audio_and_Video_Config.pdf
Right Justified. If using Altera’s UP Audio core, then the Left Justified mode must be selected. –Bit Length — allows the user to specify the number of bits of each audio sample. Valid values include 16, 20 and 24 bits for all modes, and 32 bits for …
Altera University Program Audio Core - Sharif
http://ee.sharif.edu/~microlab_t/micro/Audio.pdf
Title: Altera University Program Audio Core Author: Altera Corp. Keywords: Altera, University Program, Example System Created Date: 8/29/2012 3:13:56 PM
SDI Audio Intel FPGA IP User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug_sdi_audio-18-0.pdf
You can obtain the testbench from ip/altera/audio_ip/simulation directory. To use the testbench with the ModelSim simulator, follow these steps: 1. Open the Intel Quartus Prime software. 2. On the File menu, click the New Project Wizard. 3. Specify the working directory to ip/altera/audio_ip/simulation/megacore_build, and give a sensible
Altera University Program Video IP Cores
https://people.ece.cornell.edu/land/courses/ece5760/NiosII_doc/Video_q11.pdf
VIDEO IP CORES FOR ALTERA DE-SERIES BOARDS For Quartus II 11.0 In this example, drawing characters on the screen is implemented using the system shown in figure1. To display a character on the screen, users must specify the character location to the Character Buffer IP core.
Interfacing a processor core in FPGA to an audio …
http://www.diva-portal.org/smash/get/diva2:22246/FULLTEXT01.pdf
The following steps describe the basic design flow for using the Quartus II graphical user interface: 1. To create a new project and specify a target device or device family, on the File menu, click New Project Wizard. 2. Use the Text Editor to create a Verilog HDL, VHDL, or Altera Hardware Description Language (AHDL) design.
audio - Having FPGA to output sound on "line out" pin ...
https://stackoverflow.com/questions/30519544/having-fpga-to-output-sound-on-line-out-pin-using-verilog
Assuming you're using Nios II and either SOPC Builder or Qsys, the Altera University Program offers an IP core to control the Audio CODEC on the DE-Series boards. If you don't already have it, you can download it here (at the bottom of the page, listed as University Program Installer): https://www.altera.com/support/training/university/materials-ip-cores.html
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